1. Technical Field
Embodiments of the present disclosure may generally relate to an integrated circuit, and more particularly, to an integrated circuit and method relating to latch circuit testing.
2. Related Art
An integrated circuit including a semiconductor device includes a latch circuit to store data and signals. The latch circuit may latch and store data and signals in synchronization with a clock. The latch circuit may latch and store data and signals according to a control signal which is enabled under a preset condition.
The latch circuit included in a semiconductor device may include information on a failed cell, and may be used in replacing the failed cell with a redundancy cell in a repair operation.